48th VI-HPS Tuning Workshop (BSC, Barcelona, Spain)

Date

Monday 09 - Friday 13 February 2026

Location

The workshop will be an in loco event, specificly for teams of application developers with at least one member present on site and only a very limited amount of virtual coaching for remote participants.

Organising Institutions

Goals

This workshop organised by VI-HPS and CASTIEL2, in collaboration with POP CoE, will:

• give an overview of the VI-HPS programming tools suite
• present tools & methodology of Performance Optimisation & Productivity (POP) Centre of Excellence
• explain the functionality of individual tools, and how to use them effectively
• offer hands-on experience and expert assistance using the tools

On completion participants should be familiar with common performance analysis and diagnosis techniques and how they can be employed in practice (on a range of HPC systems). Those who prepared their own application test cases will have been coached in the tuning of their measurement and analysis, and provided optimization suggestions.

Programme Overview

Presentations and hands-on sessions are planned on the following topics:

• MAQAO performance analysis & optimisation
• Paraver/Extrae/Dimemas trace analysis and performance prediction
• Score-P instrumentation and measurement
• CUBE profile processing and exploration
• Scalasca automated trace analysis
• TALP lightweight runtime performance monitoring tool
• ... and showcase presentations/demonstrations of other tools and POP services

A brief overview of the capabilities of these and associated tools is provided in the VI-HPS Tools Guide.

The workshop will be held in English and run from 09:00 to not later than 18:00 each day, with breaks for lunch and refreshments.

Classroom capacity is limited, therefore priority may be given to applicants with parallel codes already running on the workshop computer system (MareNostrum5), and those bringing codes from similar x86_64 Linux cluster systems to work on. On-site participants are encouraged to prepare their own MPI, OpenMP and hybrid MPI+OpenMP parallel application codes for analysis. Codes using multiple GPUs via OpenACC or CUDA may also be analysed.

Programme in Detail (provisional) - all times given as CET (UTC+1)

Hardware and Software Platforms

MareNostrum5: Bull Sequana XH3000 and Lenovo ThinkSystem Linux cluster

• 6408 general-purpose compute nodes: 2 x Intel Xeon Sapphire Rapids 8480+, 56c, 2.0 GHz, 256 GB memory
• 1120 accelerated compute nodes: 2 x Intel Xeon Sapphire Rapids 8460Y+, 40c, 2.3 GHz, 512 GB DDR5 memory, 4 x NVIDIA Hopper H100 (64 GB HBM2) GPUs

The local HPC system MareNostrum5 is the primary platform for the workshop and will be used for the hands-on exercises. Course accounts will be provided during the workshop to participants without existing accounts. Other systems where up-to-date versions of the tools are installed can also be used when preferred, though support may be limited and participants are expected to already possess user accounts on non-local systems. Regardless of whichever systems they intend to use, participants should be familiar with the relevant procedures for compiling and running their parallel applications (via batch queues where appropriate).

Registration

Registration until 19 January 2026 via the course website.
There's also a technical intake questionnaire required for each application code.

The workshop will be hosted by BSC:
Barcelona Supercomputing Center
Plaça d'Eusebi Güell, 1-3, Les Corts
08034 Barcelona
Spain

Contact