Virtual Institute — High Productivity Supercomputing

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29th VI-HPS Tuning Workshop, 15-19 Oct. 2018

at HPC Centre ROMEO, Reims, France. 
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ESPT'18 Submission deadline extended

Deadline for submission of full papers is now Aug 6,... 
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ESPT'18 Travel Support from SPEXXA

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ESPT'18 Submission is open.

Deadline for submission of full papers is July 23,... 
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30th VI-HPS Tuning Workshop (BSC, Barcelona, Spain)

Date

Monday 21st - Friday 25th January 2019.

Location

The workshop will take place at Barcelona Supercomputing Center (BSC), Spain.

Organizing Institutions

BSC PRACE

Goals

This workshop organized by VI-HPS for the Spanish PRACE Advanced Training Centre hosted by Barcelona Supercomputing Center will:

  • give an overview of the VI-HPS programming tools suite
  • explain the functionality of individual tools, and how to use them effectively
  • offer hands-on experience and expert assistance using the tools

Programme Overview

Presentations and hands-on sessions are planned on the following topics:

  • Setting up, welcome and introduction
  • Paraver trace analysis tool
  • Dimemas performance prediction tool
  • Score-P instrumentation and measurement infrastructure
  • Extra-P automated performance modeling
  • Scalasca automated trace analysis toolset
  • Vampir interactive trace analysis toolset
  • TAU performance system
  • MAQAO binary analysis & optimization tool
  • ... and probably others

A brief overview of the capabilities of these and associated tools is provided in the VI-HPS Tools Guide.

The workshop will be held in English and run from 09:00 to not later than 18:00 each day, with breaks for lunch and refreshments. There is no fee for participation, however, participants are responsible for their own travel and accommodation.

Classroom capacity is limited, therefore priority will be given to applicants with parallel codes already running on the workshop computer system (MareNostrum-IV), and those bringing codes from similar systems to work on. Participants are therefore encouraged to prepare their own MPI, OpenMP and hybrid OpenMP+MPI parallel application codes for analysis.

Hardware and Software Platforms

MareNostrum-IV: Lenovo SD530 racks with a total of 3,456 compute nodes with dual Intel Xeon Platinum 8160 (Skylake) 2.1 GHz 24-core processors with 2-way SMT and 96 GB memory per node, Intel Omni-Path interconnection network, SuSE 12SP2 Linux, Intel & GCC compilers, Intel and other MPI libraries, SLURM batch software, GPFS parallel filesystem.

The local HPC system MareNostrum-IV is the primary platform for the workshop. Course accounts will be provided during the workshop to participants. Other systems where up-to-date versions of the tools are installed can also be used when preferred, though support may be limited and participants are expected to already possess user accounts on non-local systems. Regardless of whichever systems they intend to use, participants should be familiar with the relevant procedures for compiling and running their parallel applications (via batch queues where appropriate).

Participants are expected to bring and use their own notebook computers with SSH and X11 software configured to connect to the HPC systems and run interactive graphical tools.

Registration

Registration is via the PRACE training portal: the number of participants is limited and selection made based on the information provided when registering.

Contact

Judit Gimenez
Barcelona Supercomputing Center
Phone: +34 93 401-7178
Email: judit.gimenez@bsc.es

Brian Wylie
Jülich Supercomputing Centre
Forschungszentrum Jülich
Phone: +49 2461 61-6589
Email: b.wylie@fz-juelich.de

Sponsors

PRACE This workshop is a PRACE Training Centre (PTC) course, organised by Barcelona Supercomputing Center.