33rd VI-HPS Tuning Workshop (JSC, Jülich, Germany)

Date

Monday 24th - Friday 28th June 2019

Location

The workshop will take place in the Rotunda of Jülich Supercomputing Centre (JSC), building 16.4, Forschungszentrum Jülich, 52425 Jülich, Germany.

• Jülich travel and accommodation

Co-organising Institutions

Goals

This workshop organised by VI-HPS and JSC as a PRACE training event will:

• give an overview of the VI-HPS programming tools suite
• explain the functionality of individual tools, and how to use them effectively
• offer hands-on experience and expert assistance using the tools

Programme Overview

Presentations and hands-on sessions are planned on the following topics:

• Setting up, welcome and introduction
• TAU performance system
• MAQAO performance analysis & optimisation
• MUST runtime error detection for MPI
• ARCHER runtime error detection for OpenMP
• Score-P instrumentation and measurement
• Scalasca automated trace analysis
• Vampir interactive trace analysis
• Paraver/Extrae/Dimemas trace analysis and performance prediction
• MAP+PR profiling and performance reports
• JUBE script-based workflow execution environment
• Extra-P automated performance modeling
• ... and potentially others to be added

A brief overview of the capabilities of these and associated tools is provided in the VI-HPS Tools Guide.

The workshop will be held in English and run from 09:00 to not later than 18:00 each day, with breaks for lunch and refreshments. Participation is sponsored through the PRACE training centre program. All participants are responsible for their own travel and accommodation.

Participants are encouraged to prepare their own MPI, OpenMP and hybrid MPI+OpenMP parallel application codes for analysis. Codes using multiple GPUs via OpenACC, OpenCL or CUDA may also be analysed.

Programme in Detail (provisional)

Hardware and Software Platforms

JURECA: x86 Linux modular cluster system:

• Cluster: 1872 compute nodes each with dual Intel Xeon E5-2680 'Haswell' processors (2.5GHz, 12 cores per processor, 2 hardware threads per core) and 128GB RAM, Mellanox EDR InfiniBand network
  • 75 of these compute nodes additionally with two NVIDIA K80 'Kepler' GPUs (four devices per node)
• Booster: 1610 compute nodes each with single Intel Xeon Phi 7250-F 'Knights Landing' MIC processors (1.4GHz, 68 cores per processor, 4 hardware threads per core) and 96GB RAM and 16GB HBM, Intel OmniPath interconnect network
• parallel filesystem: GPFS (SCRATCH & WORK)
• software: CentOS 7 GNU/Linux; ParaStation & Intel MPI; Intel, GCC and other compilers; SLURM batchsystem

The local HPC system JURECA is the primary platform for the workshop and will be used for the hands-on exercises. Course accounts will be provided during the workshop to participants without existing accounts. Other systems where up-to-date versions of the tools are installed can also be used when preferred, though support may be limited and participants are expected to already possess user accounts on non-local systems. Regardless of whichever external systems they intend to use, participants should be familiar with the relevant procedures for compiling and running their parallel applications (via batch queues where appropriate).

Registration

Register via the PRACE training portal: the number of participants is limited and early registration is recommended.

Contact

Sponsors

This workshop is a PRACE training centre (PTC) event, organised by VI-HPS & JSC for the Gauss Centre for Supercomputing.